1. Field of the Invention
The invention relates to a flash memory, more specifically, to a flash memory with a sensing amplifier using transistors driven by coupled gate voltages for producing a load to read data.
2. Description of Background
Various microprocessor systems that are able to handle data and arrange information have become an important foundation of information development in the highly developed modern information society. The memory used to store digital data and to provide stored data for microprocessor systems is one of the most important structures in each kind of microprocessor system. A flash memory, due to electron operation, is able to store data in a non-volatile way and to read the stored data quickly and efficiently, unlike optical or magnetic storage media (such as a disc or an optical disc) that cooperates with machines so as to access data. Therefore, the flash memory with light volume and convenient and efficient operation has been utilized widely in various microprocessor systems, such as application chip systems, mobile phones, personal digital assistants, personal computers, digital cameras, etc.
Please refer to FIG. 1, which shows a circuit schematic diagram of a conventional flash memory 10. The flash memory 10 includes a memory array 14 having a plurality of memory cells (two memory cells 12A and 12B are marked in FIG. 1), each memory cell being used to store a bit data, and a transistor Q5 corresponding to each memory cell, for a reference unit. The MOS transistors Q1, Q2, Q3, Q4, inverters 16A, 16B, and a comparator 18 are organized into a sensing amplified module for reading the data stored in each memory cell. The gate of the transistor Q5 as the reference unit is biased by a fixed control voltage V0 so as to provide a fixed reference current Ip2 between its source and drain. The gate voltage of the transistor Q3 is applied by a feedback from the voltage on the node Np3 by way of the inverter 16A. Similarly, The gate voltage of the transistor Q4 is applied by a feedback from the voltage on the node Np4 by way of the inverter 16B. The transistors Q1 and Q2 whose drain and gate are shorted serve as diodes for load units, where the transistor Q1 acts as a sensing load, and both its drain and gate on the node Np1, by way of the transistor Q3, are electrically connected to the memory array 14, and the transistor Q2 on the node Np2, by way of the transistor Q4 electrically connected to the transistor Q5, acts as a reference load. The comparator 18 is capable of being formed with a differential amplifier with its differential inputs (marked as “+” and “−” in FIG. 1) respectively connected with the node Np1 and Np2 to compare the voltage on the node Np1 with the voltage on the node Np2, and the differential amplifier outputs a corresponding read signal Sr according to the compared result. The memory 10 is biased by a direct bias voltage Vd and a direct bias voltage Vg which is lower than a bias voltage Vd; the bias voltage Vg can be ground voltage (that is the zero voltage).
Each memory cell in the memory 10 has the same basic circuit configuration. Take the memory unit 12A for an example, the transistor Qm1 in the memory cell 12A is a MOS transistor with a floating gate whose gate voltage is controlled by a control voltage Vw1. The transistor Qa1 whose gate voltage is controlled by the other control voltage Vb1 acts as an access transistor. While storing data, the floating gate of the transistor Qm1 is being injected with a different amount of charge corresponding to different data. For instance, if more charge is injected into the floating gate, the transistor stores a bit data “1”; on the contrary, if less charge is injected into the floating gate, the transistor Qm1 stores a bit data “0”. The amount of the charge injected into the floating gate will influence the threshold voltage of the transistor Qm1. In FIG. 1, the more negative charge injected into the floating gate of the transistor Qm1 is, the smaller absolute value of the threshold voltage of the transistor Qm1 is. Under the circumstance of keeping the control voltage Vw1, the more negative charge within the floating gate is, the higher the conduct performance associated with the transistor Qm1 is, so that the current between the source and drain of the transistor Qm1 is greater. In other words, under the circumstance of keeping the control voltage Vw1, the bit data stored in the transistor Qm1 depends on the amount of conduct current in the transistor Qm1 between its source and drain.
When reading the data stored in each memory cell, the memory 10 determines and reads the data stored in the memory cell 10 according to the amount of current provided by the transistor with a floating gate in each memory cell. Take FIG. 1 for an example again, suppose that the memory 10 is reading the bit data stored in the memory cell 12A, the control voltage Vb1 will make the access transistor Qa1 turn on, and the transistor Qm1 will provide a driven current Ip1 between its source and drain in accordance with the amount of charge stored in the floating gate; the driven current Ip1 will pass the turn-on access transistor Qa1 to the node Np3. Meanwhile, other memory cells of the memory array 14 (like the memory cell 12B) do not provide current. For instance, the control voltage Vb2 is able to turn off the access transistor Qa2 so that the memory cell 12B will not provide current for the node Np3 to affect the data-reading for the memory cell 12A.
After passing through the node Np3, the driven current Ip1 provided by the memory cell 12A will go through the transistor Q3 and then flow into the transistor Q1. The transistor Q1 as a sensing load will generate a sensing voltage Vp1 at the node Np1 after the driven current Ip1 flows into the node Np1. For this reason, the transistor Q2 as a reference load will generate a reference voltage Vp2 at the node Np2 after receiving the reference current Ip2 provided by the transistor Q5. Please refer to FIG. 2 (with reference to FIG. 1), which shows a relation diagram of the voltage versus the current associated with the two loads shown in FIG. 1. Generally speaking, the transistor Q1 as a sensing load and the transistor Q2 as a reference load are matched. The curve 20 shows the drain voltage (that is, the nodes Np1 and Np2) versus the drain current in the two transistors Q1 and Q2, both with the form of diodes. As with the previous description, when the memory cell 12A stores different bit data respectively, it can also respectively provide the different driven current Ip1. The current Ip1(A) and Ip1(B) marked in FIG. 2 represents the two different driven voltages corresponding to different bit data. When the different driven current Ip1(A)and Ip1(B) is injected from the node Np1 into the transistor Q1, the transistor Q1 can generate different sensing voltages Vp1(A) and Vp1(B) respectively depending on the relation between the current and voltage illustrated in the curve 20. Corresponding to the two possible different sensing voltages Vp1(A) and Vp1(B) of the node Np1, the fixed control voltage V0 is used to drive the gate of the transistor Q5 so that the generated reference current Ip2 is capable of generating the fixed reference voltage Vp2 of the node Np2 driven by the transistor Q2. The comparator 18 can determine the driven current Ip1 provided by the memory cell 12A, depending on whether the voltage of the node Np1 is more than the reference voltage Vp2 with Vp1(B) or less than the reference voltage Vp2 with Vp1(A), so as to determine the bit data stored in the memory cell 12A and generate the corresponding read signal Sr to achieve the purpose of reading data.
As to the transistor Q3, the inverter 16A, 16B and the transistor Q4 shown in FIG. 1 are respectively used to cut off the memory array 14 and reference unit to prevent the load effect. The purpose of the transistor Q3 connected between the node Np1 and the node Np3 is to keep the voltage on the node Np3 a constant, not interfered by a change of the sensing voltage on the node Np1. From the view of the transistor Q3 and the sensing amplifier module, each memory cell in the memory array 14 is equivalent to a large equivalent capacitor C0 (marked in FIG. 1). If the voltage on the node Np3 changes as the voltage on the node Np1 changes, it is equal to charging or discharging the equivalent capacitor C0. The driven voltage provided by memory cells have to distribute a part of current to charge or discharge the equivalent capacitor C0 so as to change the voltage on the node Np3. In this way, such not only affects reading data, but also extends a read time until the equivalent capacitor C0 finishes being charged or discharged. Therefore, the function of the transistor Q3 is to keep the voltage on the node Np3 to prevent the negative effect caused by the large load of the equivalent capacitor C0. The operational principle of the transistor Q3 can be stated briefly as follows. When the voltage on the node Np3 rises up, the inverter 16A will relatively reduce the gate bias voltage of the transistor Q3 to increase turn-on efficiency of the p-type MOS transistor Q3, so as to reduce the voltage on the node Np3. On the contrary, if the voltage on the node Np3 falls down, the inverter 16A will increase the gate bias voltage of the transistor Q3, relatively decreasing the turn-on efficiency of the p-type MOS transistor Q3, so as to increase the voltage on the node Np3. The voltage on the node Np3 can be kept approximately constant due to the feedback control via the inverter 16A.
The defects of the conventional memory 10 are described briefly as follows. First, because the transistors Q1 and Q2 are connected with the type of diode to form a sensing load and a reference load respectively, and their current-voltage curve, shown in FIG. 2, is the parabolic curve 20 which the concave of the parabolic curve 20 indicates as upward (as the direction indicated by an arrow A1 in FIG. 2). That means even if the current difference between the two different driven currents Ip1(A) and Ip1(B) provided by memory cells is large, the corresponding voltage difference between the two sensing voltages Vp1(A) and Vp1(B) will not be large, involving that the difference between the two sensing voltages and reference voltage Vp2 (the voltage difference dV1 and dV2 marked in FIG. 2) will not be enlarged. The data-reading process of the memory 10 depends on whether the comparator 18 can distinguish the voltage between the sensing voltage Vp1 and the reference voltage Vp2 clearly. The noise margin during reading process will be reduced, easily resulting in error-readings due to noise when the voltage differences dV1 and dV2 are not large. For instance, if the voltage difference dV is too small, a small noise invading the node Np1 leads to the sensing voltage Vp1(A), originally smaller than the reference voltage Vp2, being larger than the reference voltage Vp2, and results in the comparator 18 reading the data within the memory 12A incorrectly on account of the invasion of noise.
In addition, in the conventional flash memory 10, the gates of the transistors Q1 and Q2 as load units are driven by the voltages on the nodes Np1 and Np2 respectively, and the driven state of the two transistors are separated so that the two transistors will be respectively affected by different noises, leading to the differential-driven comparator 18 easily affected by dual noises. For example, suppose that the memory cell 12A provides the driven current Ip1 (A), but the node Np1 is invaded by a positive-voltage noise, making the sensing voltage Vp1 on the node Np1 larger than the driven voltage Vp1(A) marked in the FIG. 2. Meanwhile, the node Np2 is invaded by a negative-voltage noise, making the reference voltage on the node Np2 smaller than the reference voltage Vp2 marked in the FIG. 2. Consequently, the reference voltage Vp2 is more likely to become smaller than the driven voltage Vp1, resulting in the comparator 18 incorrectly recognizing that the data of the memory cell 12A corresponds to the driven current Ip1 (B).
As with the previous statement, flash memories have been extensively utilized in kinds of microprocessor systems in need of different DC bias voltages Vd. Some of computer systems probably can provide a 6V (volt) DC bias; other portable devices may merely provide lower-than-2V DC bias. However, one of the purposes which the information industry tries to achieve is to make the same memory designation being able to work under different bias voltages. One of the defects of the conventional memory 10 is difficulty in adapting for use in different operational environments. Please keep referring to FIG. 3. Basically, the FIG. 3 shows the identical memory 10 shown in FIG. 1, but further shows the typical comparator 18 and the inverter 16A. The inverter 16A in the FIG. 3 is formed by a CMOS transistor consisting of an n-type MOS transistor Q11 and a p-type MOS transistor Q12. The comparator 18 has a differential input composed by n-type MOS transistors Q7 and Q8. The current source 22 is used to bias the differential input, p-type MOS transistors Q9 and Q10 act as active loads for taking out the read signal Sr from the node Np6. The inverter 16A and the comparator 18 both are biased by the DC bias voltage Vd and low DC bias voltage Vg.
As with the previous description, voltage on the node Np3 is kept at a constant by the transistor Q3, however, on account of the fixed voltage depending on the bias voltage of the memory array 14, no matter what the bias voltage Vd is, the voltage on the node Np3 usually can be kept to a fixed voltage. For the transistor Q12 in the inverter 16A, its bias voltage of the gate is fixed, but its source bias voltage Vd will change with different operation environments. As a result, under different operation environments, the inverter 16A, owing to various bias conditions among the ends of the transistor Q12, will be hardly biased within a better bias voltage range, and so will the inverter 16B. For this reason, the sensing voltage Vp1 on the node Np1 and the reference voltage Vp2 on the node Np2 will also approximately be kept in a fixed range under various operation environments (even though the sensing voltage Vp1 will change, the changing range relative to the difference between different bias voltages in kinds of operation environment is still much smaller). As a result, the bias voltage of the transistors Q7 and Q8 in the comparator 18 will also be kept roughly. Comparatively, each bias condition of each end of the transistors Q9 and Q10 that is mainly controlled by the bias voltage Vd, has great change under different operation environments, so that the comparator 18 is hardly kept a better bias voltage in the different operation environments. The above-mentioned factors are all reasons of why it is hard to design the conventional memory 10 to adapt to various conditions. The specific circuit must be redesigned for the conventional memory to work regularly on account of the specific operation condition. Consequently, it is a disadvantage of development and popularity for flash memories because of spending more time for circuit-designing and manufacturing time, and resources.